This invention relates to the configuration of programmable logic devices (PLDs). More particularly, the invention relates to a non-volatile electrically erasable CMOS memory cell for configuring a PLD.
A PLD is configured by programming floating gate memory cells, such as read only memory (ROM) cells, contained in a programmable array. The programmed or unprogrammed state of the memory cell is used to control whether a connection between logic elements is closed or open. Complicated sensing and amplification circuitry is required to distinguish the difference between a programmed and an unprogrammed cell, and to convert this into a voltage output swing large enough to be detected. Sensing circuitry necessary to detect such small swings occupies significant space on the die and uses substantial power, thus limiting the space and power available for other purposes.
In view of the foregoing it would be desirable to be able to provide an improved configuration cell which eliminates complicated sensing circuitry.
It would further be desirable to be able to provide an improved configuration cell in which the output voltage swings from rail to rail.
It would still further be desirable to be able to provide an improved configuration cell which utilizes essentially zero power when not switching.
It would still further be desirable to be able to provide an improved configuration cell which occupies a smaller space on the die.
It would still further be desirable to be able to provide an electrically erasable configuration cell.
It would still further be desirable to be able to provide an improved configuration cell in which the cell's ability to retain charge can be margin verified.